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DSP+FPGAĔ(sh)֞Vϵy(tng)
·Ҫܣ
·ͨ^ϵy(tng)TԽMXYɂ(g)90͆SC(j)еӼ݃xБTԿg\(yn)Ӷݔ·̖Լ·C(j)̖ͬ̎Ɍɂ(g)݃xݔ̖lʵIJɼӋ(j)(sh)͞V̎ϢĞVֵͨ^RS422ͨӍڰl(f)͵(do)Ӌ(j)C(j)ҪоƬTI TMS320F2812 DSPҪĹܞ飺 |
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- ·Ӌ(j)(sh)
- ·ӷӋ(j)(sh)
- Ӌ(j)(sh)ݔ SINCOSݔ룻
- Ӌ(j)(sh)gࡢ4lܣ
- Ӌ(j)(sh)ݔlʸ_(d) 2MHz
- 12·A/DD(zhun)Q
- ·x RS422ȫpͨӍͨ
- ÿ·Ӌ(j)(sh)256 FIFO
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DSP FirV·(yng)ùf
- Ӌ(j)(sh)·ݔ룬x4lӜpӋ(j)(sh)
- Ӌ(j)(sh)ɘӔ(sh)(j)M(jn)FIR+h(sh)֞V
- RS4222·xȫpRS422ڡʿܛO(sh)ã
- ض̖ݔ룺·ض̖ݔ룬AD590ظнӿڣ
- ̖ݔ룺3·0~10V늉ݔ룻
- (wn)l늉3·0~300V늉ӿڣ
- C(j)(q)ӣ·-65V~+65V늉ӿڣ
- Ӌ(j)(sh)ɘlʿܛO(sh)ã1KHz2KHz3KHz4KHz5KHz6KHz7KHz8KHz9KHz10KHz
- AD(sh)(j)ɘlʿ_(d)2MHz
- (sh)IO늸x
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