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DSP+FPGAĔ(sh)֞Vϵy(tng)
·Ҫܣ
·ͨ^ϵy(tng)TԽMX,Yɂ90͆SC(j)еӼ݃xБTԿg\Ӷݔ·̖Լ·C(j)̖ͬ̎,Ɍɂ݃xݔ̖lʵIJɼӋ(sh)͞V̎ϢĞVֵͨ^RS422ͨӍڰl(f)͵(do)ӋC(j),ҪоƬTI TMS320F2812 DSP,ҪĹܞ飺 |
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- ·Ӌ(sh)
- ·ӷӋ(sh),
- Ӌ(sh)ݔ SIN,COSݔ,
- Ӌ(sh)g,4lܣ
- Ӌ(sh)ݔlʸ_(d) 2MHz,
- 12·A/DD(zhun)Q,
- ·x RS422ȫpͨӍͨ
- ÿ·Ӌ(sh)256 FIFO,
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DSP FirV·(yng)ùf
- Ӌ(sh)·ݔ,x,4lӜpӋ(sh)
- Ӌ(sh)ɘӔ(sh)(j)M(jn)FIR+h(sh)֞V,
- RS4222·xȫpRS422,ʿܛO(sh)ã
- ض̖ݔ룺·ض̖ݔ,AD590ظнӿ,
- ̖ݔ룺3·0~10V늉ݔ룻
- (wn)l늉3·0~300V늉ӿ,
- C(j)(q)ӣ·-65V~+65V늉ӿ,
- Ӌ(sh)ɘlʿܛO(sh)ã1KHz2KHz,3KHz,4KHz5KHz,6KHz,7KHz8KHz,9KHz,10KHz
- AD(sh)(j)ɘlʿ_(d)2MHz,
- (sh)IO늸x,
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